Huawei's LogicFolding Architecture Targets 1.4nm Chips by 2031 Without EUV

Huawei has unveiled a chip architecture called LogicFolding that it claims will deliver 1.4nm-class transistor density by 2031 — without the extreme ultraviolet (EUV) lithography machines that US export controls have placed beyond China's reach.

The company presented the technology at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai, alongside a new design framework it calls the "Tau Scaling Law" — a proposed successor to Moore's Law that prioritizes signal speed and physical circuit stacking over transistor miniaturization.

How LogicFolding Works

Traditional chip scaling shrinks individual transistors to fit more into the same die area. Huawei's approach is different: LogicFolding physically stacks logic circuits in three dimensions, optimizing how fast electrical signals travel through them — what Huawei calls "temporal scaling." The company claims this yields a 55% increase in transistor density and a 41% improvement in power efficiency compared to conventional planar layouts.

Huawei says the development took six years and that it has already designed and mass-produced 381 chips based on Tau Scaling Law principles. Manufacturing will be handled by SMIC, China's most advanced domestic foundry, which can produce chips at the 7nm node without EUV using older deep ultraviolet (DUV) techniques.

The Commercial Roadmap

The first public application is expected in Huawei's Kirin smartphone processors, set to debut in the Mate 90 series in fall 2026. By 2030, Huawei plans to extend the architecture to its Ascend AI chips and data center clusters — a direct challenge to Nvidia's dominance in AI inference hardware inside China.

How It Stacks Up Against TSMC

TSMC, the global semiconductor foundry leader, is targeting mass production of true 1.4nm chips — its A14 process node — by 2028, ahead of Huawei's 2031 projection. TSMC's path relies on the latest-generation EUV machines from ASML, equipment Huawei cannot legally obtain under current US export rules.

Huawei's LogicFolding is therefore not a direct race against TSMC's process node roadmap. It is an architectural workaround: achieving comparable density through 3D stacking and signal optimization rather than lithographic precision. Whether stacked logic circuits deliver equivalent performance in real AI workloads — where memory bandwidth and interconnect latency matter as much as raw transistor count — is the key question that production silicon will need to answer.

What It Signals

The announcement is Huawei's most explicit challenge yet to the assumption that EUV-dependent scaling is the only credible path to advanced chips. If LogicFolding's density and efficiency claims hold in production — not just in benchmark conditions — it would represent a meaningful reduction of the gap between China's domestic semiconductor capabilities and the global frontier, achieved entirely without Western equipment. As reported by Tom's Hardware, the Mate 90 launch later this year will be the first real-world test of that claim.